Increased demand for computer memory has driven the memory industry to introduce various configurations and designs of transistors to fit more memory into a given area and, therefore, to create memory devices with increased memory density. One such memory device with the potential for increased memory density is the so-called “vertical memory” device. A vertical memory device includes an array of transistors with each transistor in the form of a pillar extending generally perpendicular to a substrate, such as a silicon substrate. Each transistor of the vertical memory device includes a silicon pillar having several doped regions. For example, a bottom region may be n-doped, a middle region may be p-doped, and a top region may be n-doped. The bottom, n-doped region may be a source region and the top, n-doped region may be a drain region. The bottom, n-doped region may extend in a first direction parallel to the substrate across multiple pillars to form a data/sense line, e.g., a bit line, for reading and writing data to the transistors. A gate material, such as a gate oxide, may be formed along a vertical sidewall of the pillar to cover the middle, p-doped region and to contact a portion of the top and bottom n-doped regions, respectively. An access line, e.g., a word line, for reading and writing data to the transistors may be formed over the gate material along the vertical sidewall of the pillar and may extend across multiple transistors in a second direction that is generally perpendicular to the first direction.
Bit lines of pillars adjacent to each other in the second direction may be separated by a trench extending in the first direction. Word lines on pillars adjacent to each other in the first direction may be separated by another trench that extends in the second direction. Such trenches may generally be filled with a dielectric, i.e., non-conductive, material, such as silicon oxide, silicon nitride, air, etc., for providing electrical isolation between adjacent bit lines and word lines, respectively.
A word line end region may be located proximate the edge of the array. Conventionally, the word line end region includes an oxide material in the form of columns, with the ends of the word lines formed along sidewalls of the oxide columns. The oxide in the word line end region may be a high quality oxide, such as a spin-on dielectric (“SOD”), which is annealed. The array may include the silicon of the pillars and another oxide material, such as an oxide formed from tetraethylorthosilicate (“TEOS”) and SOD, disposed in the trenches extending in the first direction. The oxide material in the array may be of relatively lower quality than the oxide in the word line end region. To form the conductive word lines, the trenches extending in the second direction, i.e., the word line trenches, are partially filled with conductive material to form the word lines. These word line trenches are conventionally formed by dry etching the silicon of the pillars in the array region, the oxide material in the array region, and the oxide material in the word line end region in a single etching act employing a particular chemistry. However, the silicon material and oxide material typically exhibit different etch rates when subjected to the same chemistry. In addition, a single anisotropic removal process generally forms sloped sidewalls in silicon material having an angle closer to vertical than an angle of sidewalls in oxide material. The difference in etch rates and in sidewall angles may result in uneven trench surfaces. The uneven trench surfaces may cause difficulties when forming the word line. The difference in etch rates may also cause the word line trench to be shallower in the word line end region than in the array region. The shallower depth of the word line trench in the word line end region may cause word lines formed in the word line trench to exhibit thinning or breaking. Furthermore, device performance may be negatively affected by word lines formed on the uneven trench surfaces. Cleaning the surfaces of the word line trench with aggressive cleaning agents in preparation for forming the gate oxide may aggravate these problems. However, less aggressive cleaning agents, such as water, are less effective at removing defects from surfaces of the word line trench and may leave defects that cause device failure.